1. Field of the Invention
The invention generally relates to varactors and, more particularly relates to hyper-abrupt (HA) junction varactors and a method of fabrication of HA junction varactors in CMOS, rf-CMOS, BiCMOS or analog technologies.
2. Background Description
Varactors form a class of tunable semiconductor capacitors typically derived from pn-junctions, where the pn-junction is operated in a reverse bias state. The capacitance of the varactor may be varied by adjusting the reverse bias voltage, and thus varactors are characterized by a C-V tuning curve. Varactors are especially useful in oscillator circuits, especially voltage-controlled oscillators, where the varactor tunability is used to tune the oscillation frequency of the circuit. Thus, varactors find use in cellular phones, televisions and radios, computers, active filters, and wherever a first signal is synchronized to second signal.
Varactor functioning is most easily understood in the terms of a basic capacitor. In general, a capacitor consists of two conductive plates separated by a dielectric. Opposite charges collect on the capacitor plates when a voltage potential is applied across the plates. The capacitance of the capacitor, and its ability to hold a certain amount of charge at a certain voltage, depends on the distance between the two plates, among other parameters. The larger the distance between the two plates, the less the capacitance and the less charge the capacitor can hold at a given voltage potential.
A pn-junction may function as a capacitor in the reverse bias mode because the reversed voltage potential causes charge carriers to move away from the pn-junction. The facing edges of the p and n regions collect the charge and act as the conductive plates, i.e. the anode and cathode. As the charge carriers move away from the pn-junction, a depletion region near the junction is formed which is the equivalent of a dielectric in a standard capacitor. As the voltage potential is increased, the charge carriers move farther away from the pn-junction, which is equivalent to increasing the distance between the two conductive plates of a standard capacitor. Accordingly, the capacitance of a varactor is, in part, voltage dependent and may be tuned over a particular range. The capacitance of a varactor is also dependent on other parameters such as junction area and the doping densities in the junction.
The doped region of a varactor is typically formed in semiconductor film deposited on the varactor cathode. Different doping profiles within the film may be used to achieve different capacitance-voltage tuning relationships (C-V tuning curves). The first varactors were constrained to linear doping profiles because of fabrication limitations. Such varactors have a C-V tuning curve where capacitance is proportional to the inverse cube root of the tuning voltage. As fabrication methods improved, it became possible to closely control doping profiles, and varactors with uniform doping profiles became available. The uniform doped varactors have C-V tuning curves where capacitance is proportional to the inverse square root of the bias voltage.
For some varactor applications, a linear C-V tuning curve is preferred, and thus HA junction varactors were developed. HA junction varactors have a doping profile which changes in a controlled non-linear way with density of the dopants increasing towards the junction and abruptly dropping to zero at the junction. With a suitable profile, the varactor's capacitance can be linearly dependant on bias voltage over at least a portion of the varactor's tuning curve.
HA junction varactors may be made with various methods including ion implantation and molecular beam epitaxial growth. As noted above, one of the parameters which affects the capacitance, and C-V tuning curve, of a varactor is the doping profile within the LTE (low temperature epitaxial) layer. Thus, as doping density varies, so does the C-V tuning curve of the varactor. The doping profile may be affected by, among other things, the thickness of the LTE layer. Consequently, the C-V tuning curve of varactors in a particular manufacturing batch may vary significantly from one unit to the next based on variations in the LTE layer thickness. In some examples, the C-V tuning curve has as much as a 50% variation in capacitance in the middle of the curve.
The cause of variations of the LTE layer thickness may be due to variation in initial LTE layer formation as well as changes in the LTE layer thickness caused by subsequent manufacturing steps. Such device variation due to manufacturing variation may be difficult for the design engineer to accommodate and lead to complicated circuit designs and extra steps in circuit fabrication.
Though the C-V tunability of varactors may offer the circuit designer increased freedom in designing certain circuits, known varactors have C-V tuning curves which may vary substantially from one unit to the next. Such variations are due to variations in the fabrication process, such as etching, layer formation, and doping the multiple layers of semiconductor forming the active region (cathode, collector, junction, and anode) of the varactor. In fact, varactor C-V tuning curves may vary by as much 50% from the nominal specification called for by the designer. Accordingly, circuit designs must make more complicated circuits to accommodate C-V tuning curve variation. But, such complicated fabrication processes, and circuit complexity increase the cost of varactor implementation.
Referring to FIG. 1, a related art varactor is shown. The varactor 10 has a Si (silicon) substrate 12 with an N+ subcollector 14 formed therein. The N+ subcollector 14 is positioned in a lower portion of the Si (silicon) substrate 12 and may be formed by ion implanting methods well known to those skilled in the art. For example, arsenic ions can be implanted into the Si substrate 12 to form the subcollector 14 with a dosage of about 1.4×1016 atoms/cm2 at about 40 KeV energy levels. It should be noted that there are typically diffusion areas adjacent to the N+ subcollector 14, such as, for example, at each end of the N+ subcollector 14 where some of the dopants would diffuse into the surrounding Si substrate 12. The N+ subcollector 14 functions as the cathode of the varactor 10. After forming the N+ subcollector 14 region in the substrate 12, an optional epitaxial Si layer may be formed atop the surface of the substrate 12 utilizing conventional epitaxial growing processes.
Above a portion of the N+ subcollector 14 is a collector 16. The collector 16 is formed by doping the Si substrate 12 with first conductivity type ions of either N-type or P-type. For example, the collector 16 may be formed by implanting with phosphorus ions at about 6×1012 atoms/cm2 at energy levels of about 700 KeV. Above the N+ subcollector 14 on either side of the collector 16 and next to a reach through implant 20 are isolation regions 18. The isolation regions 18 may be isolation oxides, and may further be shallow trench isolation oxides. In the case where the isolation regions 18 are shallow trench isolation oxides, the isolation regions 18 may be formed, for example, by conventional lithography, etching, and shallow trench fill methods well know to those skilled in the art.
At one end of the Si substrate 12 and between two of the isolation regions 18 is the reach-through implant 20. The reach-through implant 20 extends from a top surface of the varactor 10 into the Si substrate 12 and is in electrical communication with the N+ subcollector 14. The reach-through implant 20 may be formed using conventional methods well known in the art. Accordingly, the same ion dopant utilized to dope other regions of the varactor 10, such as used for doping the N+ subcollector region 14 may be used to form the reach-through implant 20. For example, the reach-through implant 20 may be formed with Sb (antimony) dopant with a 1.4×1014 atoms/cm2 density at about 200 KeV, or it maybe formed with P (phosphorus) dopant with a 4×1015 atoms/cm2 density at about 70 KeV.
On top of the reach-through implant 20 is a silicided region 32. The silicided region 32 serves to provide good ohmic contact to underlying reach-through implant 20, and may be formed by methods well known in the art.
On top of the collector 16 is an HA junction 24. The HA junction 24 is formed in the Si substrate 12 above the collector 16 region. The HA junction 24 is formed by doping methods well known in the art. For example, the HA junction 24 may be formed using an N-type dopant, such as Sb at a density of 5×1012 atoms/cm2 and an energy of about 40 KeV.
On top of each isolation region 18 are sacrificial layers 30. The sacrificial layers 30 serve to protect the underlying Si regions during FET processing. The sacrificial layers 30 are made of, for example, a protect dielectric such as nitride. The sacrificial layers 30 are initially deposited across substantially all of the top surface of the Si substrate 12 and protects the surface during later processing. The dielectric is etched prior to LTE processing and may leave the remaining topography. The sacrificial layers 30 may be formed, for example by PCVD (plasma chemical vapor deposition).
An LTE layer 26 is deposited over the HA junction 24. The LTE layer 26 is made from P-type Si using LTE methods well known to those of ordinary skill in the art. The LTE layer 26 is later doped with P+ type ions by necessary bipolar implants or the standard PFET source/drain ion implant. Accordingly, further bipolar processing steps are required after the HA junction 24 has been formed. Such further bipolar processing may alter the thickness, as well as other parameters, of the HA junction causing variation in the final C-V tuning curve of the varactor.
On top of the LTE region 26 is a silicided layer 34. The silicided layer 34 is formed by 1-step or 2-step silicide processes using conductive metals (i.e.: titanium, cobalt, nickel, etc.) which are well-known in the art. The silicided layer 34 serves to provide good ohmic contact to the LTE layer 26.
As noted above, either bipolar processing during and subsequent to forming the related art HA junction causes unit-to-unit manufacturing variation in related art varactor tuning curves, and such variations in varactors complicates circuit designs. Accordingly, in order to simplify the design of circuits using varactors, a fabrication process which produces varactors having less manufacturing variation in the C-V tuning curve is desirable. Additionally, HA junction varactors which have less unit-to-unit manufacturing variation in the C-V tuning curve are desired.